SAN FRANCISCO--(BUSINESS WIRE)--BrainChip, a leading provider of ultra-low power, high performance edge AI technology, has been awarded a new patent for dynamic neural function libraries, a key component of its AI processing chip AkidaTM. During a learning process, values are generated and stored in the synaptic registers of the AI device to generate a training model. Training models are themselves stored in the dynamic neural function library of the AI device, and the function library can then be used to train another device. The innovation was credited to Peter Van der Made, BrainChip founder and CTO, who has been at the forefront of computer innovation for 40 years. Van der Made is the inventor of a computer immune system at cybersecurity developer vCIS Technology, where he served as CTO and later Chief Scientist when it was acquired by Internet Security Systems and subsequently IBM.

Intel revealed the broad outlines of its new Nervana Neural Network Processor for Inference, of NNP-I for short, that comes as a modified 10nm Ice Lake processor that will ride on a PCB that slots into an M.2 port (yes, an M.2 port that is normally used for storage), at an event in Haifa, Israel two months ago. Today, the company provided further deep-dive details of the design here at Hot Chips 31, the premier venue for leading semiconductor vendors to detail their latest microarchitectures. Intel is working on several different initiatives to increase its presence in the booming AI market with its'AI everywhere' strategy. The company's broad approach includes GPUs, FPGAs, and custom ASICs to all tackle different challenges in the AI space, with some solutions designed for compute-intensive training tasks that create complex neural networks for object recognition, speech translation, and voice synthesis workloads, to name a few, and separate solutions for running the resulting trained models as lightweight code in a process called inference. Intel's Spring Hill Nervana Neural Network Processor for inference (NNP-I) 1000, which we'll refer to as the NNP-I, tackles those lightweight inference workloads in the data center.

In 2016 Intel acquired Nervana Systems in the hope of expanding beyond their traditional CPU market with more specialized ASICs. The company's first-generation Neural Network Processor (NNP) was a 28-nanometer design called Lake Crest. This chip served as a software development vehicle without making it to general availability. Intel's follow-up design is Spring Crest. It was first announced at last year's Intel AI Developer Conference.

This feature continues our series of articles that survey the landscape of HPC and AI. This final post explores AI hardware options to support the growing artificial intelligence software ecosystem. Balance ratios are key to understanding the plethora of AI hardware solutions that are being developed or are soon to become available. Future proofing procurements to support run-anywhere solutions--rather than hardware specific solutions--is key! The basic idea behind balance ratios is to keep what works and improve on those hardware characteristics when possible.

At its first AI Developer Conference, Intel announced the Nervana NNP-L1000, which is the first neural network processor (NNP) to come out of the Nervana acquisition. The chip will prioritize memory bandwidth and compute utilization over theoretical peak performance. Initially, Intel started competing with Nvidia in the machine learning (ML) chip market with its Xeon Phi architecture, which used tens of Atom cores to "accelerate" ML tasks. However, Intel must have realized that Phi alone wasn't going to allow it to catch up to Nvidia, which seems to make significant leaps in performance every year. As such, the company began looking for other options, which led it to buy Altera for its field programmable gate arrays (FPGAs), Movidius for its embedded vision processor, MobilEye for its self-driving chip, and Nervana for its specialized neural network processor.

Gara observes that, "The convergence of AI, data analytics and traditional simulation will result in systems with broader capabilities and configurability as well as cross pollination." Gara sees very aggressive hardware targets being set for this intertwined HPC and AI future, where the hardware will deliver usable performance exceeding one exaflops of double precision performance (and much more for lower and reduced precision arithmetic). He believes a user focus on computation per memory capacity will pay big dividends across architectures and provide systems software and user applications the opportunity to stay on the exponential performance growth curve through exascale and beyond as shown in the performance table below. The vision Gara presented is based on a unification of the "3 Pillars" of HPC: Artificial Intelligence (AI) and Machine Learning (ML); Data Analytics and Big Data; plus High Performance Computing (HPC). What this means is that users of the future will program using models that leverage each other and that interact through memory.

According to a study published in the journal Science, a honeycomb-pattern of tiny, nano-sized magnets that are submerged in a material known as spin ice could solve a complex computational problem in a single step. In fact, clusters of such magnet arrays function similar to a neural network: It is more "similar to how our brains work than to the way in which traditional computers process information," the researchers said. Exploiting the potential of magnets gets more difficult the closer they are located to each other as they interfere with their magnetic fields, the scientists found that their honeycomb patterns create competition between magnets and "reduces the problems caused by these interactions by two-thirds." It is good enough to store computable information and contents can be read by measuring the magnet's electrical resistance. So far, the researchers have succeeded in reading and writing data, but there has been no information about the data transfer rates. However, it seems as if speed isn't the key problem yet as their operating temperature is far more critical: At this time, the magnets only function well and "arrange themselves into patterns" at a temperature of -223 degrees Celsius.

There is an ongoing race among semiconductor companies, including the established market heavyweights and startups alike, to define the hardware platform that will run compute-intensive deep learning algorithms quickly and efficiently. Until now, NVIDIA has dominated the deep learning market with its graphics processor unit (GPU) chips, which bring massive parallelization, however field programmable gate arrays (FPGAs) and digital signal processors (DSPs) are starting to catch up. Deep learning is largely characterized by deep neural networks (DNNs) and convolutional neural networks (CNNs), which can become massively complex. Google's cat recognition neural network back had 1 billion connections using 16,000 processors. GPUs are known to achieve the best speed and throughput, around 100x faster compared to an FPGA, while FPGAs are known to have better power efficiency, around 50x better compared to a GPU.

A CCD-based processor that we call the NNC2 is presented. The NNC2 implements a fully connected 192-input, 32-output two-layer network and can be cascaded to form multilayer networks or used in parallel for additional input or output nodes. The device computes 1.92 x 10

A CCD-based processor that we call the NNC2 is presented. The NNC2 implements a fully connected 192-input, 32-output two-layer network and can be cascaded to form multilayer networks or used in parallel for additional input or output nodes. The device computes 1.92 x 10